Author : A. Ranganayakulu and K. Satya Prasad

The low power optimization techniques are very crucial for next generation wireless communication and battery powered signal processing applications. Several low power optimization techniques at circuit level and device level were implemented in past two decades to achieve low power design. However the continuously growing low power demand motivates researchers to evolve even low power designs. The architecture level low power optimization is possible for signal processing and in communication applications, considering the dynamically fluctuating signal value. The work given here presents the subword partitioning and signal value based dynamic clock gating method to achieve low power implementation without compromising on the performance. A scalable subword based clock gating scheme is presented here. A novel no-information based detection scheme is used to power down sequential and combinational logic specific to each subword. A four bit subword register is used for validating the proposed low power scheme. The circuit is designed at schematic level and extracted netlist is simulated with 130 nm CMOS model file. The simulation results for clock gating scheme demonstrated average power optimization of 21% when compared to simulation results without clock gating scheme. The future work is aimed to achieve higher power savings for developing combinational logic with power gating feature.

Keywords: Low power, data driven clock gating, dynamic power, CMOS 130 nm, CMOS, average power analysis

Article published in International Journal of Current Engineering and Technology, Vol.5, No.3 (June-2015)