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Implementation of 16X16 SRAM Memory Array using 180nm Technology

Author : Preeti S Bellerimath and R. M Banakar

Pages : 288-292
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Static Random access memory (SRAM) are useful building blocks in many applications such as a data storage embedded applications, cache memories, microprocessors. Large SRAM arrays that are widely used as cache memory in microprocessors and application-specific integrated circuits can occupy a significant portion of the die area. For high density circuits such as SRAM arrays, which are projected to occupy more than 90% of the SoC area in the next 10 years. In an attempt to optimize the performance of such chips, large arrays of fast SRAM help to boost the system performance. However, the area impact of incorporating large SRAM arrays into a chip directly translates into a higher chip cost. Balancing these requirements is driving the effort to minimize the footprint of SRAM cells. As a result, millions of minimum-size SRAM cells are tightly packed making SRAM arrays the densest circuitry on a chip. In this paper an effort is made to design 16X16 SRAM memory array on 180nm technology. For high-speed memory applications such as cache, a SRAM is often used. Access time, speed, and power consumption are the three key parameters for an SRAM memory design(SRAM). The integrated SRAM is operated with analog input voltage of 0 to 1.8v. The 16×16 SRAM memory has been designed, implemented & analysed in standard UMC180nm technology library using Cadence tool.

Keywords: SRAM, Access time, Cadence, power consumption, UMC180

Article published in the Proceedings of National Conference on ‘Women in Science & Engineering’ (NCWSE 2013), SDMCET Dharwad




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