Author : Meenu Roy and N.Kirthika

High performance Arithmetic Coder architecture is proposed in this paper for image compression. This arithmetic coder architecture is used in Set Partitioning. In Hierarchical Trees for further compression of the Discrete Wavelet Transform decomposed images. The architecture is based on a simple context model. Simple context model results in regular access pattern during reading the wavelet transform coefficients which is convenient to the hardware implementation. The arithmetic coder contains four core’s to process different contexts and there is an out-of-order execution mechanism for different types of context is proposed that helps to allocate the context symbol to the idle arithmetic coding core with different order that of input. Several dedicated circuits such as common bit detector are used in the architecture to further improve the throughput. Common bit detector can unroll the renormalization stage of the arithmetic coding. For low and high updated values, the carry look-ahead adder and fast multiplier divider are also employed in the architecture which shortens the critical path. An adaptive clock switch mechanism is used which can stop some invalid bit planes clock for the power saving purpose according to the input images. Experimental result proves that the arithmetic coder architecture with four internal cores having similar architecture gives better performance as compared with single core architecture.

Keywords: Arithmetic Coder(AC), Set Partitioning In Hierarchical Trees(SPIHT), Discrete Wavelet Transform(DWT), Context model, Common Bit Detector(CBD), Carry Look-ahead Adder, Fast multiplier/ divider, Critical path, Adaptive clock switch.

Article published in International Journal of Current  Engineering  and Technology, Vol.4,No.3 (June- 2014)