Author : M.Dhruvakumar, M.C.Chandrashekhar and M.Z.Kurian

Wireless technology is emerged has the vibrant research areas in the modern communication industry. The IEEE 802.16e has defined a standard called mobile WiMAX and emerged as the latest wireless technology that has promised to offer Broadband Wireless Access over long distance. The OFDM technique is used in WiMAX to obtain high data rate in addition to reducing the effects of inter symbol interference and inter channel interference. This paper proposes an algorithm to model the Address Generation circuitry of WiMAX Deinterleaver using Verilog on FPGA platform with all code rates and modulation schemes of IEEE 802.16e standard. The implementation of floor function in FPGA is very difficult in IEEE 802.16e standard. Hence the requirement of floor function can be eliminated by using a simple mathematical algorithm. The main scope of the work is to concentrate on performance improvement by reducing interconnection delay, lesser power consumption, and efficient resource utilization by comparing with prevailing technique.

Keywords: Deinterleaver/Interleaver circuit, Wireless systems, QPSK, QAM

Article published in International Journal of Current  Engineering  and Technology, Vol.4,No.3 (June- 2014)