Author : Sangam Lal Jaiswal, Anil Kumar, A.K.Jaiswal, Rajeev Paulus and Mayur Kumar

The current interest is focused principally on the low voltage and low power digital CMOS usage requiring deep submicron devices. For deep submicron devices Silicon on Insulator (SOI) MOSFETS are better to their counterparts using bulk CMOS. There is a concern about the aptness of SOI for various electrical parameters especially in the submicron domain. This paper Weigh the performance of SOI at different technological nodes. The focus of our paper is on leakage current, threshold voltage and subthreshold conduction of SOI fabrication in the submicrometer scope. We have fabricated soi n-MOSFET using Silvaco-Athena and carried out simulations for leakage current, threshold voltage and subthreshold conduction at 1micron, 91nm and 64nm of technological nodes. Silvaco-Athena design and simulation results using Atlas are presented, that shows soi technology is still better in the submicron region. Kink effect analysis is also carried out.

Keywords: MOSFET, SILVACO-ATHENA, ATLAS, SOI, Subthreshold Conduction, Submicron Technology

Article published in International Journal of Current  Engineering  and Technology, Vol.4,No.3 (June- 2014)