Author : M.Roopa Nandini, P.Mor and J.M. Keller

The choice of the CMOS logic to be used for implementation of a given specification is usually dependent on the optimization and the performance constraints that the finished chip is required to meet. Several design options exist for CMOS combinational gates. One of the reliable, low-power design uses complementary static gates, where as high performance circuits uses dynamic logic styles which is more suitable for high speed. The performance of static logic is better than dynamic logic for designing basic logic gates like NAND and NOR however it is observed through studies that dynamic logic performance is better for higher fan in and complex logic circuits and also with the increasing level of integration, high performance, high speed and low power dissipation have become the mandatory requirements for any logic design. This paper presents a comparative study of CMOS static and dynamic logic.

Keywords: Static CMOS circuits, Dynamic CMOS circuits, Strong Zero, Strong One, Logic synthesis

Article published in International Journal of Current Engineering and Technology, Vol.6, No.3 (June-2016)