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To Study and Characterisation of N N+ N Nanowire Transistor (Junctionless) using 2D ATLAS Simulator


Author : Akash Kumar Gupta, Anil Kumar and A.K. Jaiswal

Pages : 2203-2206
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Abstract

A polysilicon gated N N+ N silicon substrate junctionless nanowire transistor purposed in this paper. Conduction mechanisms in junctionless nanowire transistors (gated resistors) are compared to inversion-mode and accumulation-mode MOS devices uses bulk conduction.The current drive is controlled by dopping concentration concentration. Its characteristics demonstrated and compared with conventional N-MOS transistor using 2D-ATLAS simulator. The result shows that junctionless transistor has a number of desirable features, such as linear variation of Id with control gate voltage, low leakage current and threshold, effect of different control gate voltage studied and demonstrated in the paper.

Keywords: N N+ N transistor (3N), Threshold voltage, Leakage current, Back current, 2D-ATLAS

Article published in International Journal of Current  Engineering  and Technology, Vol.4,No.3 (June- 2014)

 

 

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