Author : Y. Narasimha Rao, G.Samuel Vara Prasada Raju and Penmetsa V Krishna Raja

In many generic systems it is challenging to reduce the load resulted by many coprocessors, which are used to provide special functions like arithmetic operations, signal processing and many other applications. The speed of processors or coprocessors mainly depends on its internal arithmetic circuits like multipliers in ALU. Many signal processing and scientific computers are demanding multiple number of high speed multipliers on single chip. But this increasing instruction cycle time which further causes decrease in system performance. Maintaining higher throughput in arithmetic operations is important to achieve the desired performance in many real-time applications. One of the key arithmetic operations in such applications is to achieve faster multiplication. Vedic Mathematics is one of the fast and low power multiplier. In this paper the Vedic Multiplier is designed by Urdhva Tiryagbhyam (UT) technique. In the present work the multiplier design and the Multiplier performance was analyzed with various existing fast adders like Carry Look Ahead Adder (CLA), Carry Select Adder (CSLA), Parallel prefix adder (PPA). Here the Vedic multiplier is constructed with different fast adders and analyzed with FPGA using Xilinx Synthesis Tool (XST).

Keywords: Vedic Multiplier, Fast Adders, High speed circuits, system performance, ALU

Article published in International Journal of Current  Engineering  and Technology, Vol.4,No.3 (June- 2014)