Author : Tanesh Kumar, B Pandey and Teerath Das

In this paper Voltage Scaling is used to design energy efficient Gaussian FIR Filter. This design is implemented on Kintex-7 FPGA, XC7K70T device, -3 speed grade and FBG676 package. Among all powers in FPGA, it is observed that Logic Power have maximum Power reduction of 100% at 5GHz and IO power have minimum power reduction of 2.25% at 1 THz, while the voltage is scaled from 1.0 to 0.2V. Clock power is reduced up to 86.11%, 87.14%, 87.10% and 87.26% and Leakage power is reduced to up to 50.39%, 66%, 82.78% and 82.78%, when the FIR filter is operated at 5GHz, 50GHz, 500GHz and 1 THz frequencies respectively and voltage is scaled down from 1.0V to 0.2V.

Keywords: Voltage Scaling, FIR Filter, Energy Efficient Design, FPGA, Power Dissipation