News Updates Thursday 19th Oct 2017 :
  • Welcome to International Press Corporation, world's leading publishers, We have served more than 10000+ authors
  • Articles are invited in engineering, science, technology, management, industrial engg, biotechnology etc.
  • Paper submission last date of Sept/Oct 2017 extended to 20 Oct 2017, Submit online or at editor.ijcet@inpressco.com
  • Our journals are indexed in University of Regensburg Germany, Google Scholar, Cross Reference data bases
  • Applications for reviewers are invited and can be sent directly to concerned editor's mail

Voltage Scaling Based Energy Efficient FIR Filter Design on FPGA


Author : Tanesh Kumar, B Pandey and Teerath Das

Pages : 200-203
Download PDF
Abstract

In this paper Voltage Scaling is used to design energy efficient Gaussian FIR Filter. This design is implemented on Kintex-7 FPGA, XC7K70T device, -3 speed grade and FBG676 package. Among all powers in FPGA, it is observed that Logic Power have maximum Power reduction of 100% at 5GHz and IO power have minimum power reduction of 2.25% at 1 THz, while the voltage is scaled from 1.0 to 0.2V. Clock power is reduced up to 86.11%, 87.14%, 87.10% and 87.26% and Leakage power is reduced to up to 50.39%, 66%, 82.78% and 82.78%, when the FIR filter is operated at 5GHz, 50GHz, 500GHz and 1 THz frequencies respectively and voltage is scaled down from 1.0V to 0.2V.

Keywords: Voltage Scaling, FIR Filter, Energy Efficient Design, FPGA, Power Dissipation

 

 

Call for Papers
  1. IJCET- Sept/Oct-2017 Issue

    Submission Last Date extended to
    20 Oct 2017
  2. IJTT-Sept-2017
  3. IJAIE-Sept-2017
  4. IJCSB-Sept-2017
  • Inpressco Google Scholar
  • Inpressco Science Central
  • Inpressco Global impact factor
  • Inpressco aap

International Press corporation is licensed under a Creative Commons Attribution-Non Commercial NoDerivs 3.0 Unported License
©2010-2017 INPRESSCO® All Rights Reserved