Author : Shilpa Shrigiri and Yojna Bellad

Gating of the clock signal in VLSI chips is nowadays a mainstream design methodology for reducing switching power consumption. As a consequence many techniques have been proposed to reduce power dissipation. This paper gives the circuit level design of a 16-bit binary counter implemented with clock gating at nibble (4-bit) level. It also gives the power comparison between the normal implementation and the one with clock gating in terms of power. Mentor Graphics tool is used to obtain the gate level hardware design and its simulations. This analysis stresses the use of clock gating as an efficient power reduction technique.

Keywords: Low power design, binary counter, flip-flops, clock gating, power dissipation, clock distribution network, EDA tools, overhead.

Article published in the Proceedings of National Conference on ‘Women in Science & Engineering’ (NCWSE 2013), SDMCET Dharwad