Implementation of an Image Thinning Algorithm using Verilog and MATLAB
Pages : 333-337
Image thinning is a signal transformation that converts a thick digital image into a thin digital image or obtains its skeleton form. The skeleton expresses the structural connectivites of the main component of a object and is one pixel in width. Skeletonization reduces the original image into a more compact representation. A basic method of skeletonization is thinning. In this paper image thinning operation has been implemented on a binary image of 128 x 128 pixels using Zhang Suen’s thinning algorithm. The proposed work is designed using MATLAB 7.12 and also synthesized by mapping on Virtex 5 in Xilinx ISE for understanding the hardware complexity. Simulation results are obtained in terms of waveforms in ISim Xilinx ISE Simulator and the output text file of the hardware system is converted to an image format using MATLAB. Performance measurement is carried out between Zhang – Suen’s thinning algorithm and MATLAB command for image thinning in terms of Thinning Rate (TR).
Keywords: Image thinning, skeletonization, Zhang – suen’s algorithm, digital image processing, Verilog, MATLAB, Hardware Description Language (HDL), iteration.
Article published in the Proceedings of National Conference on ‘Women in Science & Engineering’ (NCWSE 2013), SDMCET Dharwad