Author : Rajeshwari Mathapati, Geetanjali Kamble and S.K.Shirakol

Large SRAM arrays that are widely used as cache memory in microprocessors and application-specific integrated circuits can occupy a significant portion of the die area..In an attempt to optimize the performance of such chips, large arrays of fast SRAM help to boost the system performance. The demand for static random- access memory (SRAM) is increasing with large use of SRAM in mobile products, System On-Chip (SoC) and high-performance VLSI circuits.70% of the System On-Chip (SoC) uses SRAM memory. SRAM is significant component used for the cache memory in microprocessors, main frame computers, engineering workstations and memory in hand-held devices due to high speed and low power consumption. The main objective of this project is to design and implement Dual Port SRAM Memory using 180nm CMOS technology. The work includes designing of write and read circuit. The Dual Port SRAM is capable of storing 2 bits with operating voltage of 1.8v.To design and implement SRAM Memory array Standard GPDK180(General Purpose Design Kit) technology library is used. The proposed work is designed using Cadence Tool.

Keywords: Dual port SRM etc.

Article published in the Proceedings of National Conference on ‘Women in Science & Engineering’ (NCWSE 2013), SDMCET Dharwad