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Design of High Speed 128 bit AES Algorithm for Data Encryption


Author : Sumalatha Patil M and Mala L M

Pages : 338-343
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Abstract

With the fast progression of data exchange in electronic way, information security is becoming more important in data storage and transmission. Cryptography is the study of mathematical techniques related to aspects of information security such as confidentiality, data integrity, entity authentication and data origin authentication. In data and telecommunications, cryptography is necessary when communicating over any unreliable medium, which includes any network particularly the internet. The Advanced Encryption Standard (AES) is the newly accepted symmetric cryptography standard for transferring block of data securely. The AES algorithm defined by the National Institute of Standard and Technology (NIST) of United States has been widely accepted. AES involves the sequence of four primitive functions: Sub Bytes, Shift Rows, MixColumn and Add Round Key. This paper presents the design of a 128 bit encryptor using AES Rijndael Algorithm for 128 bit data encryption. These designs were described using VerilogHDL. Xilinx ISE 14.2 software is used for synthesis.

Keywords: AES, Cryptography, Encryption, MixColumn, Key Expansion, S-box, Security, Verilog.

Article published in the Proceedings of National Conference on ‘Women in Science & Engineering’ (NCWSE 2013), SDMCET Dharwad

 

 

 

 

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