Author : Rohini

As the feature size is continuously decreasing and chip integration is increasing, bus connections have become a dominating factor in determining the overall quality of a System on Chip. Long global wires also cause many design problems, such as routing traffic, scalability, latency and throughput. Network-on-Chip NoCs are an evoluting architecture to be used in future systems, due to its increased performance, reusability and scalability. A NoC is a set of interconnected switches, with IP cores[1] connected to these switches. Routing plays an important role in determining latency and delay of router in NoC. In this paper mesh based router architecture using minimal West First Routing Algorithm is presented. The delay and latency performance of routers have been analyzed through simulation.

Keywords: ASIC, NoC, PE, RTL, SoC

Article published in the Proceedings of National Conference on ‘Women in Science & Engineering’ (NCWSE 2013), SDMCET Dharwad