Author : Omkar A. Shastri , Shubhangini Ugale and Vipin Bhure

This paper proposes a 32 bit RISC processor with a parallel processing floating point multiplier for high speed
operations. The processor consists of blocks namely, Instruction fetch block, Instruction decode block and the
execution block. The execution block will comprise of the parallel processing floating point multiplier so that high
speed inputs can be provided thereby improving the accuracy of the system. As the processor is 32 bit, single precision floating point format will be used. Furthermore power gating technique will be used to lower the power consumption of the processor. We use 3 stage pipelining which involves instruction fetch module, instruction decode module and execution module. All the blocks are designed using VHDL hardware description language.

Keywords: RISC, Floating point multiplier, Power gating, VHDL.

Article published in International Journal of Current Engineering and Technology, Vol.6, No.2 (April-2016)