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Performance Analysis of Router for Network on Chip

Author : Farhina T. Ansari, Bharati B. Sayankar and Pankaj Agrawal

Pages : 685-687
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Major drawback of bus based communication system is that the loading effect becomes more if the complexity of the system is increased which drops the speed further. Ad-hoc routing of wires results in backend complications, lower performance and higher power consumptions. Network on Chip (NoC) has been adopted as a new promising solution for its extensibility and power efficiency. The fundamental unit of Network on Chip is the router. In this paper, we proposed a router module with wormhole switching concept. The router module is described at RTL level using VHDL and simulated in Xilinx ISE 13.1 simulator.

Keywords: System on Chip, Network on Chip, Routers, Switching Techniques, Arbitration.

Article published in International Journal of Current  Engineering  and Technology, Vol.3,No.2 (June- 2013)





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