Author : Amiya Karmakar, Deepshikha Mullick, and Amitabha Sinha

Enhancement of the performance and speed of the Digital Signal processing processors are the major challenge due to its wide spread real world applications. At the same time high quality (less erroneous) and high speed digital inputs are required for these DSP Processors. Hence the high performance and high speed A/D or D/A converter design is the another major issue for performance and speed matching with these DSP processors.  In this paper a novel technique is introduced to enhancement the performance of the Sigma Delta modulator using Least Mean Square (LMS) algorithm. This LMS algorithm is used to minimize the quantization error and hence the performance enhancement. The circuit implementation requires limited additional circuits for the proposed technique. For design and implementation of the proposed sigma delta modulator, a Simulink model is constructed for the oversampled Sigma Delta Modulator with applied LMS algorithm. This model is verified by two types of simulations like Matlab and ModelSim. The proposed architecture is also synthesized for FPGA implementation.

Keywords: Analog to Digital Converter (ADC), Configurable Logic Block (CLB), Digital Signal Processing (DSP), Field Programmable Gate Array (FPGA), Harvard architecture, Least Means Square (LMS), Look up Table (LUT), Power Spectral Density (PSD).

Article published in International Journal of Current  Engineering  and Technology, Vol.4,No.1 (Feb- 2014)