News Updates Wednesday 24th Oct 2018 :
  • Welcome to INPRESSCO, world's leading publishers, We have served more than 10000+ authors
  • Articles are invited in engineering, science, technology, management, industrial engg, biotechnology etc.
  • Paper submission last date of Sept/Oct 2018 extended to 25 Oct 2018, Submit online or at
  • Our journals are indexed in NAAS, University of Regensburg Germany, Google Scholar, Cross Ref etc.
  • DOI is given to all articles

FPGA Implementation of FIR Filter Design with Optimization of Adder Tree & Constant Multiplication

Author : I.Arivazhagan, G.Annalakshmi and R.Kuppuraj

Pages : 2128-2137
Download PDF

Finite Impulse Response filter is mostly used in the digital signaling processing (DSP) applications. In FIR most important parameters are complexity, cost, and power consumption. While the research focus of resolve the thus parameter to be reduced. To use the Multiple Constant Multiplication (MCM) for optimize the adder tree in the filter. In this paper we have identified the resource minimization problem in the scheduling of adder-tree operations in MCM blocks by using Mixed Integer Programming (MIP).Result shows that up to 11.09% reduction of area and 7.66% reduction of power can be achieved on the top of already optimized adder/subtractor network of the MCM block.

Keywords: MIP, MCM, CSD, adder tree, digital signal processing, FIR etc

Article published in International Journal of Current Engineering and Technology, Vol.5, No.3 (June-2015)


Call for Papers
  1. IJCET- Sept/Oct 2018 Issue

    Submission Last Date
    25 Oct
  2. DOI is given to all articles
  3. Current Issue
  4. IJTT-Dec-2018
  5. IJAIE-Dec-2018
  6. IJCSB-Dec-2018
  • Inpressco Google Scholar
  • Inpressco Science Central
  • Inpressco Global impact factor
  • Inpressco aap

International Press corporation is licensed under a Creative Commons Attribution-Non Commercial NoDerivs 3.0 Unported License
©2010-2018 INPRESSCO® All Rights Reserved