Author : Ashwini D. Dhanadravye and Samrat S. Thorat

Universal Asynchronous Receiver Transmitter (UART) is widely used serial data transmission protocol to support full duplex communication. This paper presents the design of 9 bit UART module based on VHDL. The design of 9 bit UART specialized with automatic address and data differentiator in the character itself thus allowing the incoming data to be transferred directly to the destination, in case address matches. UART design mainly consists of three important modules which are receiver module, transmitter module and baud rate generator. The UART design with VHDL as design language can be integrated into the Field Programmable Gate Array to achieve reliable, compact & stable data transmission. It’s significant for the design of System on Chip. The whole design simulated using Active-HDL simulation tool and implemented onto FPGA board using Quartus II software.

Keywords: Asynchronous serial communication, Quartus II, simulation, VHDL, UART

Article published in International Journal of Current  Engineering  and Technology, Vol.4,No.3 (June- 2014)