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FPGA Based FIR Filter Design for Enhancement of ECG Signal by Minimizing Base-line Drift Interference


Author : Digvijay J. Pawar and P. C. Bhaskar

Pages : 1775-1778
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Abstract

Baseline noise removal from Electrocardiogram (ECG) signal is a blind source separation problem. Various noises affect the measured ECG signal. Major ECG noises are base-line noise, power-line noise, electrode contact noise, muscle noise. Baseline noise distorts the low frequency segment of ECG signal. The low frequency segment is S-T segment. This segment is very important and has the information related to heart attack. There are various techniques to remove this noise from noisy ECG signal. Efficient removal of baseline noise might give us certain information that are hidden from the doctors until now which may save the life of a person. Baseline drift noise occurs due to respiratory signal and body movements. Respiratory signal wanders between 0.15Hz and 0.5Hz frequencies. One of the most common methods to remove baseline drift interference is high pass filtering. This research work is based on High pass filtering of ECG signal to remove this baseline wander while preserving the low frequency ECG clinical information. The results of different filter design techniques like equiripple, least square and various windowing methods are compared using MATLAB simulation tool and best suited technique is used for further implementation on FPGA platform.

Keywords: ECG, Baseline Noises, FIR filters, Window methods, signals to noise ratio (SNR), FPGA.

Article published in International Journal of Current  Engineering  and Technology, Vol.3,No.5(Dec- 2013)

 

 

 

 

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