Author : Shailesh S. Nichat and Shrikant J. Honade

 
In last two decades, many efficient algorithms and architectures have been introduced for the design of low complexity bit-parallel Multiple Constant Multiplications (MCM) operation which dominates the complexity of many digital signal processing systems. On the other hand, little attention has been given to the digit-serial MCM design that offers alternative low complexity MCM operations at the cost of an increased delay. In this topic, we address the problem of optimizing the gate-level area in digit-serial MCM designs and introduce high level synthesis algorithms, design architectures, and a computer aided design tool. The proposed optimization algorithms for the digit-serial MCM architectures in the design of digit-serial MCM operations and finite impulse response filters yields better performance compared with multiple Constant multiplier using Common Sub-expression Elimination(CSE) algorithm with high efficiency.

Keywords: Gate-level area optimization, multiple constant multiplications, Common Sub-expression Elimination (CSE) algorithm, Graph Base (GB) algorithm

Article published in International Journal of Current  Engineering  and Technology, Vol.3,No.2 (June- 2013)