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Design of Commutative Cryptography Core with Key Generation for Distributed FPGA Architecture

Author : R. Ambika, S. Ramachandran, K.R. Kashwan

Pages : 3519-3527
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Data security during communication is one of the predominant issues in modern multiple transceiver based communication. In this paper, we have presented a highly robust commutative cryptography core for distributed FPGA architecture called commutative RSA with Key generation. The commutative RSA algorithm has been developed using parallelization of Montgomery multiplication with high radix exponential modular multiplication scheme to suit FPGA implementation. The architectural design not only ensures authentication among multiple transceivers or MIMO but also reduces overheads caused due to key exchange process. The CRSA algorithm with key generation has been realized with multiple FPGA cores using VHDL. The design has been simulated using Modelsim 5.5e and synthesized using Xilinx Design Suite 14.3 targeted on Virtex-5, xc5vfx70t-2ff1136 FPGA and Vivado 12.3, Virtex-7, xc7vx330tffg1157-2L. The results obtained illustrates that the proposed architecture offers high computational efficiency with minimum overheads and memory occupancy even at higher frequency rate. The designed system works at 292 MHz in Vivado and at 199 MHz in ISE 14.3 platforms and would be compatible with a standard real time data communication hardware interface.

Keywords: FPGA, Linear Feedback Shift Register, MIMO, Montgomery multiplication, RSA, Security

Article published in International Journal of Current Engineering and Technology, Vol.4, No.5 (Oct-2014)


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