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Clock Tree Synthesis based on Wire length Minimization Algorithm


Author : Neeraja John and Ramesh P.

Pages : 1987-1989
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Abstract

Clock Distribution Network is to be designed carefully to optimize many performance criteria like power, area and delay. The reduced process size necessitates better distribution strategies and algorithms. In this paper, a hierarchical clock network design by making use of the diagonal routes is presented. Buffers are introduced to get perfect pulse width, duty cycle and latency.

Keywords: Clock Tree Synthesis, Exact zero skew, Buffer insertion, delay minimization, Matlab, Spice

Article published in International Journal of Current Engineering and Technology, Vol.5, No.3 (June-2015)

 

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