Author : Ranjeet Kumar Verma, Anil Kumar and A.K. Jaiswal

A polysilicon gated N+ N N+ silicon substrate transistor purposed in this paper. Its characteristics demonstrated and compared with conventional N-MOS transistor using 2D-ATLAS simulator. The result shows that 3N transistor has a number of desirable features, such as linear variation of Id with control gate voltage, low leakage current and threshold, effect of different control gate voltage studied and demonstrated in the paper.

Keywords: N+ N N+ transistor (3N), Threshold voltage, Leakage current, Back current, 2D-ATLAS

Article published in International Journal of Current  Engineering  and Technology, Vol.4,No.3 (June- 2014)