Author : Palagani Yellappa, S K. Mahaboob Basha and K. Neelima

Network-on-Chip (NoC) is composed of three main building blocks links, routers and network interfaces (NIs). In NoC links are the major power dissipation sources and self-switching, coupling-switching activities are responsible for link power dissipation. This paper introduces set of efficient data encoding and decoding schemes for reduction of link power dissipation, delay. First self switching is reduced by checking the switching transition and then the coupling between the links is checked and ensured that the power consumption is reduced. In this paper, we refer to the end-to-end encoding technique, this technique takes advantage of the pipeline nature of the wormhole switching technique. Especially the decoding schemes are focused on reducing hardware and delay. This paper proposing the concept of on-chip networks, sketches a data encoding & decoding internal views and analyzes the power and delay reduction of both encoding & decoding schemes in Xilinx Spartan3E family (XC3S500E-5FG320).

Keywords: Coupling switching activity, Data encoding, Data decoding, NoC, Power reduction and verilog HDL.

Article published in International Journal of Current Engineering and Technology, Vol.5, No.4 (Aug-2015)