Author : Archana Parutabadi and Channakka L.

This paper presents the design technique for a sigma-delta modulator in a standard 0.18μm CMOS technology. This circuitry performs the function of an analog-to-digital converter. A first-order 1-bit sigma-delta (Σ-Δ) modulator is designed, simulated and tested using Cadence 0.18 μm CMOS process technology with power supply of 1.8 V through Cadence. The modulator is proved to be robustness, the high performance in stability .The simulation are compared with those from a traditional analog-to-digital converter to prove that sigma-delta is performing better with low power and area.

Keywords: Sigma delta (ΣΔ) modulator, Cadence Virtuoso Suite Tool, DRC (Design Rule Check), ERC (Electrical Rule Check), LVS (Layout Versus Schematic) and RCX (Resistor Capacitor extract), Layout area, dynamic power and total power.

Article published in the Proceedings of National Conference on ‘Women in Science & Engineering’ (NCWSE 2013), SDMCET Dharwad