Author : Kavana V Hegde, Yasha Jyothi M Shirur and Veena S Chakravarthi

Power dissipation is one of the biggest challenges and is the main concern in VLSI systems. In this paper, a new style of logic design based on Shannon’s decomposition theorem is used to reduce the power consumption. The paper considers various types of designs using Shannon’s expansion theorem to reduce the power consumption in digital system and a design that enables to achieve substantial reduction in power consumption is developed. The concept is been applied to the multiple digital circuits. And it is proved that the proposed concept have major power reduction when the system is complex. Almost 40% of power reduction was achieved when applied to 128:1 MUX. The design is simulated using Xilinx. The circuit synthesizability is verified using RTL compiler of Cadence. The synthesis reports are compared to arrive at a conclusion. This concept can easily be applied even to Design for testability [DFT], especially during Scan test where there is big requirement of power reduction.

Keywords: Verilog, Xilinx, Shannon’s expansion theorem, RTL complier, Design for Testability [DFT]

Article published in the Proceedings of National Conference on ‘Women in Science & Engineering’ (NCWSE 2013), SDMCET Dharwad